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[SourceCode] FPGA信号发生多波形程序

Description: FPGA的DDS的HDL程序，还有生成的波形MIF表
Platform: | Size: 14833714 | Author: jxa2010 | Hits:

[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE

Description: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Platform: | Size: 5120 | Author: 莫汉伟 | Hits:

[VHDL-FPGA-Verilog] dds_fpga

Description: DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS
Platform: | Size: 180224 | Author: 孙洪亮 | Hits:

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] DDS_generator

Description: DDS锯齿波发生器： 开发平台：maxplus＋FPGA 功能： 输出X路扫屏锯齿波。频率可用键盘精确控制，设置多个挡位；可水平移动波形；-DDS sawtooth generator : Development Platform : maxplus+ FPGA functions : So output X Lu Ping Sawtooth. Keyboard can be used precision frequency control, multiple gear; Mobile waveform can level;
Platform: | Size: 852992 | Author: shiyj | Hits:

[Other] wave_generator_1

Description: 在采用FPGA开发DDS时，常需要写波表，十分麻烦...己通过调试。-in FPGA development DDS, often need to write wave table, very troublesome ... had passed through debugging.
Platform: | Size: 18432 | Author: 张三 | Hits:

[Books] DDStheuseofFPGAsina

Description: DDS技术应用于FPGA实现正弦波（周期信号）的产生-DDS technology for FPGA sine wave (periodic signals) have
Platform: | Size: 14336 | Author: 1 | Hits:

[SCM] DDS

Description: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Platform: | Size: 2745344 | Author: 张新 | Hits:

[SCM] jcyf

Description: 本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。-The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to SPCE061A Singlechip for process control and scheduling core mission FPGA for external expansion, internal self-system bus, address decoding using the entire translated code approach. DDS has built internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal.
Platform: | Size: 178176 | Author: 郑坤 | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.
Platform: | Size: 827392 | Author: liqijun | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: 这是quicklogic公司的直接频率合成（DDS）Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
Platform: | Size: 22528 | Author: jinzhoulang | Hits:

[assembly language] EXPT84_DAC2ADC

Description: FPGA+DA转换,ALTERA公司FPGA与DA实现,DA转换功能!-FPGA+ DA conversion, ALTERA company FPGA and DA realize, DA conversion!
Platform: | Size: 16384 | Author: 19820521 | Hits:

[Communication-Mobile] DDFS_PLL_10DA_with51

Description: FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
Platform: | Size: 627712 | Author: huang | Hits:

[Embeded-SCM Develop] NIosIIStart

Description: NIosII软处理器快速入门,ALTERA FPGA的NIOSII入门指导-Quick Start NIosII soft processor, ALTERA FPGA s NIOSII Getting Started guide
Platform: | Size: 617472 | Author: leedong | Hits:

[Software Engineering] dds_an_quicklogic

Description: 该文档是QUICKLOGIC的一篇关于用FPGA实现DDS的设计指导。-The document is an article on using the QuickLogic FPGA design guidance to achieve DDS.
Platform: | Size: 46080 | Author: cobain | Hits:

[Other] fenping

Description: FPGA里面的分频器相关资料-FPGA divider inside information
Platform: | Size: 690176 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verilog编程，利用FPGA实现两路正弦波的信号输出，也可以扩展成六路正弦输出-Verilog programming, the use of FPGA realize two sinusoidal output signals can also be extended into a six-way sinusoidal output
Platform: | Size: 4792320 | Author: 陈剑 | Hits:

[SCM] DDS-320-func

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。
Platform: | Size: 460800 | Author: hangyinli | Hits:
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